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Preliminary W83196S-14 100 MHZ CLOCK FOR BX CHIPSET (2 CHIP)
1. GENERAL DESCRIPTION
The W83196S-14 is a Clock Synthesizer which provides all clocks required for high-speed RISC or CISC microprocessor. Twelve different frequency of CPU, and PCI clocks are externally selectable with smooth transitions. The W83196S-14 provides I2C serial bus interface to program the registers to enable or disable each clock outputs and choose the 0.5% center type spread spectrum to reduce EMI. The W83196S-14 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI CLOCK outputs typically provide greater than 1V/nS slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1V/nS slew rate into 20 pF loads as maintaining 50 5% duty cycle. The fixed frequency outputs as REF, 24 MHz, and 48 MHz provide better than 0.5V/nS slew rate.
2. FEATURES
* Supports Pentium II CPUs with I C * 12 sets of CPU frequencies selection * 2 CPU clocks (one free running CPU clock) * 7 PCI synchronous clocks(one free running PCI clock) * Optional single or mixed supply:
2
(VDDR = VDDCore = VDDP = VDD4 = 3.3V 5%) (VDDA = VDDC = 2.5V 5%)
* Skew form CPU to PCI clock 1.5 to 4.0 nS, CPU leads. * CPU clock jitter less than 200 pS * PCI_F, PCI1: 6 clock skew less than 500 pS * Smooth frequency switch with selections from 66.8 MHz to 150 MHz CPU * I C 2-Wire serial interface and I C read back * 0.5% center type spread spectrum function to reduce EMI * Programmable registers to enable/stop each output and select modes
2 2
(mode as Tri-state or Normal )
* MODE pin for power management * 48 MHz for USB * 24 MHz for super I/O * Packaged in 28-pin SOP
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Publication Release Date: March 1999 Revision A1
Preliminary W83196S-14
3. BLOCK DIAGRAM
VDDR X1 X2 REF2X
XTAL OSC
VDDA
IOAPIC VDDC
SEL100/66#
Spread Spectrum /2/3/4
PLL1
STOP
VDDC VDDP PCI clock Divder STOP 6
CPUCLK_F CPUCLK1
SEL48* MODE*
Latch
PCICLK(1:6) PCICLK_F
CPU_STOP# PCI_STOP# SDATA* SCLK*
Contro Logic Config. Reg. PLL2
VDDP
VDD4 48MHz 24/48MHz VDD4
4. PIN CONFIGURATION
Xin Xout VssP PCICLK_F PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDDP PCI_STOP#/PCICLK5 CPU_STOP#/PCICLK6 VDD4 48MHz/Mode* 24/48MHz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VssR REF2X/SEL48* VDDR VDDA IOAPIC VDDC CPUCLK_F CPUCLK1 VDDCore VssC SDATA SDCLK SEL100/66# Vss4
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Preliminary W83196S-14
5. PIN DESCRIPTION
IN - Input OUT - Output I/O - Bi-directional Pin # - Low active * - Internal 250k pull-up
5.1 Crystal I/O
SYMBOL Xin Xout PIN 1 2 I/O IN FUNCTION Crystal input with internal loading capacitors and feedback resistors.
OUT Crystal output at 14.318 MHz nominally.
5.2 CPU, PCI Clock Outputs
SYMBOL CPUCLK_F CPUCLK1 PCICLK [ 1:4 ] PCICLK_F PCICLK5/ PCI_STOP# PCICLK6/ CPU_STOP# 11 I/O 10 I/O If Mode* =1 (default), then this pin is a PCICLK5 buffered output of the crystal. If Mode* = 0 , then this pin is PCI_STOP# input used in power management mode for synchronously stopping the all CPU clocks. If Mode* = 1 (default), then this pin is a PCICLK6 clock output. If Mode* = 0 , then this pin is CPU_STOP # and used in power management mode for synchronously stopping the all PCI clocks. 4, 5, 6, 7, 8 PIN 22, 21 I/O FUNCTION OUT Low skew (<250 pS) clock outputs for host frequencies such as CPU, Chipset and Cache. VDDC is the supply voltage for these outputs. OUT Low skew (<250 pS) PCI clock outputs.
5.3 I2C Control Interface
SYMBOL SDATA* SDCLK* PIN 18 17 I/O I/O IN
2
FUNCTION Serial data of I C 2-wire control interface Serial clock of I2C 2-wire control interface
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Publication Release Date: March 1999 Revision A1
Preliminary W83196S-14
5.4 Fixed Frequency Outputs
SYMBOL SEL100/66# IOAPIC REF2X / SEL48* PIN 16 24 27 I/O IN O I/O FUNCTION CPU clock frequency select pin. Provides 14.318 fixed frequency. Internal 250k pull-up. Latched input for SEL48* at initial power up. SEL48* = 1 , pin14 is 24 MHz SEL48* = 0 , pin14 is 48 MHz Reference clock during normal operation. 24/48MHz 48MHz/Mode* 14 13 O I/O Frequency is set by the state of pin 27 on power up. Internal 250k pull-up. 48 MHz output for USB during normal operation. Latched input for Mode* at initial power up. Mode* = 0 , then pin10 is PCI_STOP#, and pin11 is CPU_STOP#. Mode* = 1.(default), pin10 is PCICLK5 and pin11 is PCLCLK6.
5.5 Power Pins
SYMBOL VDDCore VDDP VDDA VDDC VDD4 VDDR VssC, VssR, Vss4, VssP PIN 20 9 25 23 12 26 FUNCTION Power supply for core logic and PLL circuitry. Connect to 3.3V supply. Power supply for PCICLK_F and PCICLK 1:6. Connect to 3.3V supply. Power supply for IOAPIC output, Connect to 2.5V supply Power supply for CPUCLK _F and CPUCLK1. Connect to 2.5V supply. Power supply for 48mhz USB clock . Connect to 3.3V supply. Power supply for 14.318mhz ISA clock . Connect to 3.3V supply.
3, 15, 19, Circuit Ground. 28
6. FREQUENCY SELECTION
SEL100/66# 1 0 CPUCLK_F, CPUCLK1 100 MHz 66.8 MHz PCI 33.3 MHz 33.3 MHz
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Preliminary W83196S-14
7. FUNCTIONAL DESCRIPTION
7.1 Power Mamagement Functions
All clocks can be individually enabled or disabled via the 2-wire control interface. On power up, external circuitry should allow 3 ms for the VCOs to stabilize prior to enabling clock outputs to assure correct pulse widths. When MODE = 0, pins 10 and 11 are inputs (PCI_STOP#), (CPU_STOP#), when MODE = 1, these functions are not available. A particular clock could be enabled as both the 2wire serial control interface and one of these pins indicate that it should be enabled. The W83196S-14 may be disabled in the low state according to the following table in order to reduce power consumption. All clocks are stopped in the low state, but maintain a valid high period on transitions from running to stop. The CPU and PCI clocks transform between running and stop by waiting for one positive edge on PCICLK_F followed by negative edge on the clock of interest, after which high levels of the output are either enabled or disabled. CPU_STOP# 0 0 1 1 PCI_STOP# 0 1 0 1 CPUCLK1 LOW LOW RUNNING RUNNING PCICLK1:4 LOW RUNNING LOW RUNNING CPUCLK_F& PCICLK_F RUNNING RUNNING RUNNING RUNNING XTAL & VCOs RUNNING RUNNING RUNNING RUNNING
7.2 2-Wire I2C Control Interface
The clock generator is a slave I2C component which can be read back the data stored in the latches for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-wire control interface allows each clock output individually enabled or disabled. On power up, the W83196S-14 initializes with default register settings, and then it is optional to use the 2-wire control interface. The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high during normal data transfer. There are only two exceptions. One is a high-to-low transition on SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a low-to-high transition on SDATA while SDCLK is high used to indicate the end of a data transfer cycle. Data is always sent as complete 8-bit bytes followed by an acknowledge generated. Byte writing starts with a start condition followed by 7-bit slave address and a write command bit [1101 0010], command code checking [0000 0000], and byte count checking. After successful reception of each byte, an acknowledge (low) on the SDATA wire will be generated by the clock chip. Controller can start to write to internal I2C registers after the string of data. The sequence order is as follows: Bytes sequence order for I2C controller:
Clock Address A(6:0) & R/W
Ack
8 bits dummy Command code
Ack
8 bits dummy Byte count
Ack
Byte0,1,2... until Stop
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Publication Release Date: March 1999 Revision A1
Preliminary W83196S-14
Set R/W to 1 when read back the data sequence is as follows:
Clock Address A(6:0) & R/W
Ack
Byte 0
Ack
Byte 1
Ack
Byte2, 3, 4... until Stop
7.3 Serial Control Registers
The Pin column lists the affected pin number and the @PowerUp column gives the state at true power up. Registers are set to the values shown only on true power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. After that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and acknowledged. Register 0 to Register 2 are referred to the Winbond SDRAM buffer(W83178S/179J) drivers. 7.3.1 Register 3: CPU Frequency Select Register (1 = Enable, 0 = Stopped) BIT 7 6 5 4 3 2 1-0 @POWERUP 0 0 0 0 0 0 00 PIN Reserved SSEL2 ( Frequency table selection by software via I2C) SSEL1 ( Frequency table selection by software via I2C) SSEL0 ( Frequency table selection by software via I2C) 0 = Selection by SEL100/66# 1 = Selection by software I2C - Bit 6:4 and Register 7 Bit0 Reserved Bit1 0 0 1 1 Bit0 (See Function Table) 0 1 0 1 Normal Test Mode 0.5% center type Spread Spectrum enabled Tristate DESCRIPTION
(I) Default Frequency table selection by software via I2C (When Register 7 Bit 0 = 0 ) SSEL2 0 0 0 0 1 1 1 1 SSEL1 0 0 1 1 0 0 1 1 SSEL0 0 1 0 1 0 1 0 1 CPU, SDRAM (MHZ) 68.5 75 83.3 66.8 103 112 133.3 100 PCI (MHZ) 34.25 37.5 41.6 33.4 34.25 37.3 44.43 33.3 REF2X (MHZ) 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318
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Preliminary W83196S-14
(II) Default Frequency table selection by software via I2C (When Register 7 Bit 0 = 1) SSEL2 0 0 0 0 SSEL1 0 0 1 1 SSEL0 0 1 0 1 CPU, SDRAM (MHZ) 124 150 140 133 PCI (MHZ) 41.3 (CPU/3) 37.5 (CPU/4) 35 (CPU/4) 33.3 (CPU/4) REF2X (MHZ) 14.318 14.318 14.318 14.318
FUNCTION TABLE
FUNCTION Description Tri-State Normal CPU Hi-Z See table PCI Hi-Z See table OUTPUTS REF2X Hi-Z 14.318 IOAPIC Hi-Z 14.318
7.3.2 Register 4 : CPU , 48/24 MHz Clock Register (1 = Enable, 0 = Stopped) BIT 7 6 5 4 3 2 1 0 @POWERUP 0 1 0 0 0 1 0 1 PIN 14 21 22 Reserved 24/48 MHz (Active/Inactive) Reserved Reserved Reserved CPUCLK1 (Active/Inactive) Reserved CPUCLK_F (Active/Inactive) DESCRIPTION
7.3.3 Register 5: PCI Clock Register (1 = Enable, 0 = Stopped) BIT 7 6 5 4 3 2 1 0 @POWERUP 1 1 1 0 1 1 1 1 PIN 4 11 10 8 7 6 5 DESCRIPTION PCICLK_F (Active/Inactive) PCICLK6 (Active/Inactive) PCICLK5 (Active/Inactive) Reserved PCICLK4 (Active/Inactive) PCICLK3 (Active/Inactive) PCICLK2 (Active/Inactive) PCICLK1 (Active/Inactive)
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Publication Release Date: March 1999 Revision A1
Preliminary W83196S-14
7.3.4 Register 6: IOAPIC and REF2X Clock Register ( 1 = Enable, 0 = Stopped ) BIT 7 6 5 4 3 2 1-0 @POWERUP 0 0 1 0 0 0 11 PIN 24 27 Reserved Reserved IOAPIC (Active/Inactive) Reserved Reserved Reserved Bit1 1 1 0 0 Bit0 1 0 1 0 REF2X Drive strength 2X Drive strength 1X Drive strength 1X Tri-state DESCRIPTION
7.3.5 Register 7: Additional Register BIT 7 6 5 4 3 2 1 0 @POWERUP x x x x x x x 0 PIN Reserved Reserved Reserved Reserved Reserved Reserved Reserved Frequency select bit for different CPU/PCI frequency table setting by Register3 bit4-bit6 (SSEL0-SSEL2) DESCRIPTION
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Preliminary W83196S-14
8.0 SPECIFICATIONS
8.1 Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD). PARAMETER Voltage on Any Pin with Respect to GND Storage Temperature Ambient Temperature Operating Temperature SYMBOL VDD, VIN TSTG TB TA RATING -0.5V to +7.0V -65 C to +150 C -55 C to +125 C 0 C to +70 C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
8.2 AC Characteristics
VDDR = VDDCore = VDDP = VDD4 = 3.3V 5%, VDDA = VDDC = 2.5V 5% , TA = 0C to +70C
PARAMETER Output Duty Cycle CPU to PCI Offset Skew (CPU-CPU), (PCIPCI) Cycle to Cycle Jitter CPU Absolute Jitter Jitter Spectrum 20 dB Bandwidth from Center Output Rise (0.4V ~ 2.0V) & Fall (2.0V ~0.4V) Time Overshoot/Undershoot Beyond Power Rails Ring Back Exclusion
SYM.
MIN. 45
TYP. 50
MAX . 55 4 250 200 500 500
UNITS % nS ps ps ps KHz nS
TEST CONDITIONS Measured at 1.5V 15 pF Load Measured at 1.5V 15 pF Load Measured at 1.5V
tOFF tSKEW tCCJ tJA BWJ tTLH tTHL Vover VRBE
1
0.4
1.6
15 pF Load on CPU and PCI outputs 22 at source of 8 inch PCB run to 15 pF load Ring Back must not enter this range.
0.7 0.7
1.5 2.1
V V
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Publication Release Date: March 1999 Revision A1
Preliminary W83196S-14
8.3 DC Characteristics
VDDR = VDDCore = VDDP = VDD4 = 3.3V 5%, VDDA = VDDC = 2.5V 5% , TA = 0C to +70C
PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage IOL = 1 mA Output High Voltage IOH = -1 mA Output Low Current
SYM. VIL VIH IIL IIH VOL VOH IOL
MIN.
TYP.
MAX. 0.8
UNITS Vdc Vdc A A mVdc Vdc
TEST CONDITIONS
2.0 -25 10 50 3.1 27 20.5 40 50 25 57 53 85 74 37 55 55 87 88 44 97 139 140 152 76 97 189 155 188 94
CPU_F, CPU1 CPU_F, CPU1 CPU_F,CPI1 PCI_F,PCI1:6 IOAPIC REF2X 48,24 MHz CPU_F,CPI1 PCI_F,PCI1:6 IOAPIC REF2X 48,24 MHz
mA mA mA mA mA mA mA mA mA mA
Output High Current
IOH
25 31 40 54 27
8.4 Buffer Characteristics
8.4.1 Type 1 Buffer for CPUCLK_F and CPUCLK1 PARAMETER Pull-up Current Min. Pull-up Current Max. Pull-down Current Min. Pull-down Current Max. Rise/Fall Time Min. Between 0.4V and 2.0V Rise/Fall Time Max. Between 0.4V and 2.0V SYMBOL IOH (min) IOH (max) IOL (min) IOL (max) TRF (min) TRF (max) 0.4 1.6 27 MIN. -27 -27 TYP. MAX. UNITS mA mA mA mA nS nS TEST CONDITIONS Vout = 1.0V Vout = 2.0V Vout = 1.2V Vout = 0.3V 10 pF Load 20 pF Load
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Preliminary W83196S-14
8.4.2 Type 2 Buffer for IOAPIC PARAMETER Pull-up Current Min. Pull-up Current Max. Pull-down Current Min. Pull-down Current Max. Rise/Fall Time Min. Between 0.7V and 1.7V Rise/Fall Time Max. Between 0.7V and 1.7V SYM. IOH (min) IOH (max) IOL (min) IOL (max) TRF (min) TRF (max) 0.4 1.8 28 -29 MIN. TYP. MAX. UNITS mA mA mA mA nS nS TEST CONDITIONS Vout = 1.4V Vout = 2.7V Vout = 1.0V Vout = 0.2V 10 pF Load 20 pF Load
8.4.3 Type 3 Buffer for REF2X, 24 MHz, 48 MHz PARAMETER Pull-up Current Min. Pull-up Current Max. Pull-down Current Min. Pull-down Current Max. Rise/Fall Time Min. Between 0.8V and 2.0V Rise/Fall Time Max. Between 0.8V and 2.0V SYM. IOH (min) IOH (max) IOL (min) IOL (max) TRF (min) TRF (max) 1.0 4.0 29 MIN. -29 -23 TYP. MAX. UNITS mA mA mA mA nS nS TEST CONDITIONS Vout = 1.0 V Vout = 3.135V Vout = 1.95 V Vout = 0.4 V 10 pF Load 20 pF Load
8.4.4 Type 5 Buffer for PCICLK (1:6,F) PARAMETER Pull-up Current Min. Pull-up Current Max. Pull-down Current Min. Pull-down Current Max. Rise/Fall Time Min. Between 0.8V and 2.0V Rise/Fall Time Max. Between 0.8V and 2.0V SYM. IOH (min) IOH (max) IOL (min) IOL (max) TRF (min) TRF (max) 0.5 2.0 30 38 MIN. -33 -33 TYP. MAX. UNITS mA mA mA mA nS nS TEST CONDITIONS Vout = 1.0V Vout = 3.135V Vout = 1.95V Vout = 0.4V 15 pF Load 30 pF Load
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Publication Release Date: March 1999 Revision A1
Preliminary W83196S-14
9. OPERATION OF DUAL FUCTION PINS
Pin13 is dual function pins and are used for selecting different functions in this device (see Pin description). During power up, these pins are in input mode (see Figure 1), therefore, and are considered input select pins. When VDD reaches 2.5V, the logic level that is present on these pins are latched into their appropriate internal registers. Once the correct information are properly latched, these pins will change into output pins and will be pulled low by default. At the end of the power up timer (within 3 ms) outputs starts to toggle at the specified frequency.
2.5V
VDD
#13 48/MODE*
Output tri-state
Output pull-low Within 3 mS
Input All other clocks
Output tri-state Output pull-low
Output
Each of these pins are a large pull-up resistor ( 250 K @3.3V ) inside. The default state will be logic 1, but the internal pull-up resistor may be too large when long traces or heavy load appear on these dual function pins. Under these conditions, an external 10 K resistor is recommended to be connected to VDD if logic 1 is expected. The same 10 K connection to ground if a logic 0 is desired. The 10 K resistor should be place before the serious terminating resistor. Note that these logic will only be latched at initial power on. If optional EMI reducing capacitor are needed, they should be placed as close to the series terminating resistor as possible and after the series terminating resistor. These capacitor has typical values ranging from 4.7 pF to 22 pF.
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Preliminary W83196S-14
VDD
Series 10 KW Terminating Resistor Device Pin 10 KW
Clock Trace EMI Reducing Cap Optional
Ground
Ground
Programming Header
VDD Pad 10K Device Pin
Ground Pad Series Terminating Resistor
Clock Trace EMI Reducing Cap Optional Ground
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Publication Release Date: March 1999 Revision A1
Preliminary W83196S-14
10. ORDERING INFORMATION
PART NUMBER W83196S-14 PACKAGE TYPE 28-pin SOP PRODUCTION FLOW Commercial, 0 C to +70 C
11. HOW TO READ THE TOP MARKING
W83196S-14 28051234 814GBB
1st line: Winbond logo and the type number: W83196S-14 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 G B B 814: packages made in '98, week 14 G: assembly house ID; A means ASE, S means SPIL, G means GR BB: IC revision
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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Preliminary W83196S-14
12. PACKAGE DIMENSIONS
28-pin SOP
Headquarters
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792646 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale.
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Publication Release Date: March 1999 Revision A1

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